News
23/07/2010 Akya announces membership of Cadence’s new System Realisation Alliance
Cadence’s forward-looking industry alliance simplifies movement from high-level design synthesis to chip designs.
Selby, UK, 23rd July, 2010 – Akya, the market leader in dynamically reconfigurable logic (DRL) IP technology today announces that it has become a member of Cadence’s System Realization Alliance. Akya’s membership of this body further underlines its long- term commitment to accelerating and simplifying the process of designing silicon using its flexible, powerful ART DRL IP technology.
The System Realization Alliance aligns members to improve productivity in developing and verifying systems including software and silicon. The broad-ranging alliance spans the scope of system development with members providing tools, design and verification IP, services and training. Cadence itself has underlined the following key objectives for the System Realization Alliance: - Increasing tool usability and interoperability. - Defining open methodologies built on industry standards.
- Enabling the creation of reusable system-level design and verification IP.
- Proliferating methodology usage through training.
- Simplifying methodology adoption and assisting customer success through services.
One of Akya’s key objectives is to simplify the process of moving from high-level chip synthesis in languages such as C to realised designs. As well as the development of new tools, this will hinge on the development of advanced design flows such as TLM-driven design – one of the core drivers for the Cadence System Realization Alliance.
Other members of the alliance include ARM and TSMC.
“We’re particularly grateful to Cadence for having the far-sightedness to co-ordinate an industry body such as this,” commented Colin Dente, CEO of Akya. “We’ve been saying for a while that one of the main barriers towards innovation is lengthy design and verification times. Bringing market-leading companies together in this way is the ideal way to reduce design and verification times, thus bringing more complex and differentiated products to market. Together we are stronger.’
Full details of the Cadence System Realization Alliance are available here.
22/04/2010 Akya launches ART2.1 DRL IP with up to 2x speed improvement
Akya, exhibiting ART2.1 at ESC Silicon Valley, also developing C Compiler to further shorten design times.
Selby, UK, April 22nd, 2010 – Akya today announces the launch of ART2.1, the next generation of its leading dynamically reconfigurable logic (DRL) IP with several major innovations. ART2.1 can now run up to twice as fast as its predecessor and will work significantly better with code generated by high-level-language compilers. With these and many other improvements ART2.1 is highly optimised for the implementation of high-performance, flexible digital signal processing applications.
DRL technology, with its huge advantages over other programmable technologies in terms of power, speed and size, has a variety of applications in everything from portable media players to telecommunications backbones. ART brings these advantages within the reach of every chip designer. ART technology makes the design and implementation of reconfigurable chips simpler by separating dataflow circuitry from control logic, and by providing a large, ready-made library of IP building blocks for designers to work with.
ART simplifies the process of designing dynamic circuitry with two high-level, custom- made design languages; one for data flow and one for control. Akya provides training in the simple-to-use ART2 architecture compiler (Artac), as well as comprehensive support, providing an easy route for training staff in the new languages.
Akya has introduced two main innovations to ART2.1. The first is a modified configuration instruction pathway, which allows up to 2x system clock speed compared to ART2.0. The second is an augmented Interconnect Sequencer instruction set, improving the performance of code generated by, for example, C compilers.
As part of its ongoing efforts to facilitate faster, simpler design of DRL chips Akya is even developing its own ‘ART2C’ C compiler. This is in recognition of the huge role C plays in modern system design, and the need to offer a level of abstraction equivalent to that available when designing traditional architecture.
“We’re now offering DRL IP that is even faster and more efficient than last year, and more able to handle C-compiled code,” said Akya CEO Colin Dente. “C plays a huge role in the world of digital signal processing, and we’re delighted to offer a product that is optimised to handle it. ART2.1 not only enables digital signal processors with flexible logic, but also devices that are smaller, faster and more power-efficient than software DSPs. DRL technology can also significantly reduce the risk of semiconductor manufacture. With today’s fast-moving market, specifications for products can change after expensive tape-outs have taken place.
With ART2.1 OEMs can cheaply mass-produce a single core product, for example a media player semiconductor, and differentiate from product to product by adjusting the DRL element. Bug-fixes and updates can be fixed after tapeout, and even over-the-air, where appropriate.” Companies designing in ART2 will save themselves the considerable time and expense of having to develop a reconfigurable technology in-house, with all of the attendant risk. Akya has many years of customer-side and EDA experience, and delivers fast, efficient and well-supported implementations of flexible logic.
ART2.1, along with attendant demonstration devices, is available now. Akya will be on- hand to discuss ART2.1 at ESC Silicon Valley, San Jose, April 26th-29th (Stand 2331).